With the increasing use of packet-based transmissions, many network devices such as switches and routers now use network processors. Network processors may be thought of as general purpose processors with special features or architectures to enhance and/or to optimize packet processing within networks. These processors are typically adapted to be more flexible and more easily programmable with regard to their packet processing features.
Much of the work of network processors involves activities such as accessing data structures for a particular data flow through the network device. They may also determine which of a set of parallel interfaces should receive packets from a particular input or corresponding to a particular flow. For example, a packet enters the network device and the processor needs to determine to which flow that packet belongs. This involves a cluster of information such as the source address of the packet, the destination address, etc.
This cluster of information is used to access static or dynamic per-flow state and other information such as a table of input interface attributes etc. for whatever entities inside the network device are involved in the flow for that packet. Reducing this cluster of information down to a more manageable size is useful to speed up access of the information needed to route the packet on its way. For example, ten or more bytes of source address, destination address, and protocol information might be reduced to a three-byte key which could be used to access state information for that particular flow.
This reduction is generally accomplished using hashing and modulo functions, in which a hash of the information is further reduced modulo the size of a table, and is then used as the access key to the table. However, hashing, particularly high-quality hashing which distributes the data sufficiently randomly across the desired address space, may be very time-consuming and require either more circuitry which raises costs, or more processor cycles which lowers performance.
In addition, many network processors may not have division units used to carry out the modulo reduction of the hash result. Division is generally an expensive operation to implement in hardware, uses too many cycles to be implemented efficiently in software, and is not generally needed for any packet-processing operations other than modulo reduction of the hash result. Therefore, network processor architectures usually do not include division capabilities.